For those who are so inclined, I'm currently messing around with a Xilinx Spartan 2, which apparently has 50,000 programmable gates. Out of curiosity, what do chips today need when it comes to this sort of thing? I'm sort of curious because 50,000 seems like an unreachable number with the simple stuff I've been doing at the moment.

It has been one really long time since I was into designing chips, but I seem to remember that some of the stuff that we did for term projects were in the low thousands of gates. With 50k gates, I think you could easily fit an 8 bit microprocessor. Looking at some stuff online, it looks like a 16 bit microcontroller such as the 68HC11 (http://www.gmvhdl.com/hc11core.html) is just a little bit too large. One of the schools I went to was heavily into ARM (http://en.wikipedia.org/wiki/ARM_architecture). I worked for a division of GM that made radios, instrument clusters and engine/body computers and mostly built things out of 6805, 68HC11 and 68332 controllers. One fascinating part of the 68332 (http://en.wikipedia.org/wiki/Freescale_683XX) was the TPU (http://www.freescale.com/files/microcontrollers/doc/user_guide/MC68336376UM11.pdf?fpsp=1&WT_TYPE=Users%20Guides&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation) which was basically a CPU that operated on time instead of on numbers.

Calculations based on your statement of "spartan 2" and "50k" implies an XC2S50 (page 2 of this datasheet (http://www.xilinx.com/support/documentation/data_sheets/ds001.pdf)).
And the remarks on the Green Mountain page (page 4 of this datasheet (http://www.xilinx.com/support/documentation/data_sheets/ds022-1.pdf)) implies that their core uses 1/10th of a gate array that's 5 times bigger than your gate array, so with routing, it just might fit, maybe.

All the stuff I did would be horribly obsolete by today's standards. What sort of projects do you have in mind?

Genuine curiosity really, I've been working through some basic projects as research for one of my professors who is interested in embedded systems development. When he gave me the spec sheet for the board, I saw the number of programmable gates and it got me to wondering what a production chip would need, but I didn't really know where to start looking.

That time based CPU concept is pretty slick actually, I'd imagine the set of problems it can solve would be pretty specialized though.

Mainly I'm looking to get familiar with how the software we're using works, as well as what the capabilities of the board are.

I asked my brother to comment on this since it's right up his alley as he's a gEEky engineer type. Here is his response.

Interesting: What got you looking at this?

Well the short of it is “not all gates are the same”. Xilinx uses two interconnected Configurable Logic Blocks (CLBs). If memory also serves me right the Xilinx CLBs have four inputs, which gives a total of 16 logic states. The reason that not all logic gates are the same is because the software used to fit the logic into the CLBs first simulates the logic functions and then breaks the simulated logic functions down in to states that can be placed in a CLB. With this approach, a CLB could hold around 30 gates (a value I like us in determining logic gates in a FPGA) in a perfect world. Reviewing the datasheet for the Xilinx Spartan 2 family, a 50K gate part has 384 CLBs which will give around 130.2 gates per CLB. This is a value I find hard to believe – again not all logic gates are the same. I never use logic gates when looking at an FPGA for this very reason. The number of logic gates really depends on how well the fitter works to get the simulated logic functions into a 16 state, four input look up table or CLB.

Now as far as a processor being implemented in a FPGA is concerned, there are number of things that affect the microcontroller FPGA design. Some FPGA (Xilinx Spartan family) have distributed RAM. This RAM may or may not be available it all depends on the fitter again and routing (more routing than fitting). If there is not enough RAM, than a CLB can be used, but using a FPGA’s CLBs for RAM greatly reduces the logic gate capability of the device. The microcontroller will need both RAM, ROM, I/O and Registers – all can be considered memory.

Now to the questions of can a 50K gate Spartan be used to implement a microcontroller. A 8051 microcontroller has been implement on a Spartan 2 with 50K gates. I’m not sure how many gates and how much RAM was used but I expect that external memory would be needed to make the 8051 fully functional. It is much easier to implement RISC type cores in a FPGA because RISC by their very natural require less resources RAM, ROM, and Gates to implement. The 8051 is a CISC Core.

Open Cores (http://www.opencores.org) have number of microcontroller and other FPGA projects that can be reviewed to for implementation requirements in a FPGA.

But, remember not all gates are the same and if you read information on FPGAs from Xilinx, Altera, Lattice-semiconductors and others you would see that each claim a large number of gates can in fit in their similar CLB structures, so gates are a not a good indication of an FPGAs capability. It boils down to the fitter software used to compress the logic design into a look up tables, CLBs, distributed RAM, and I/O cells (FlipFlops). For many cases, the FlipFlop count of an FPGA and how fast a flip can flop is the most import determining factor in choosing a FPGA.

Please let me know if you have any questions.

Regards.
Robert

Thanks for the help Fild. Some of it is over my head at the moment, but it gives me stuff to read up on! If I remember right, flip flops are used to make cache memory because it can change states faster than regular RAM bits can, correct?

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Hi Kris,

I saw that the guy responded back to you. He is correct, but this is not what I meant for the FPGA. Each CLB pair drives a number of flip flops so that synchronous logic can be implemented in FPGA otherwise all the logic would be asynchronous which is and can be a very bad thing. Especially for FPGAs because it requires time to look up the output on the CLBs, so the flip flops allows the CLBs to be clocked out at a known clock rate.

Robert

From memory, the 68332 was used in the body controller (http://www.freescale.com/webapp/sps/site/application.jsp?nodeId=02WcbfwDTFKVxh) for the late 80s/early 90s Corvette (http://en.wikipedia.org/wiki/Chevrolet_Corvette_C4), and 8 of the TPU channels were used for the ABS (http://en.wikipedia.org/wiki/Anti-lock_braking_system) system (http://auto.howstuffworks.com/auto-parts/brakes/brake-types/anti-lock-brake.htm) (1 input and 1 output per wheel). Motorola (now Freescale) and Delco Electronics (now Delphi Electronics) were very closely related, and DE licensed many of the chips that Motorola made (DE has a very large IC fab facility in Kokomo, IN). I may be wrong, but I believe that the 68332 was designed for Delco, and that Motorola was permitted to sell it to anyone they wanted to. Some of the other members of the 683xx family included the 68360 which was designed to be a router/switch for T1 lines. All the members of the 683xx family used a core CPU that was basically a 68020 (think of it as about the same as a '386).

If you want to know more about automotive electronics, this (http://www.amazon.com/Understanding-Automotive-Electronics-William-Ribbens/dp/076801221X/) is the latest version of the book I used to teach from. The audience was mostly car mechanics and the technicians who repaired dashes, radios and engine/body computers; so the mechanics already understood the engine bits and needed to learn the electronics bits, while the technicians understood the electronics and didn't really understood how they dealt with the engine and brakes.

Spark plug timing is really simple PWM, and since engine RPM doesn't change rapidly, it doesn't need any sophisticated electronics like a TPU. Whereas anti-lock braking or traction control needs to react in milliseconds.
If I remember right, flip flops are used to make cache memory because it can change states faster than regular RAM bits can, correct? By "regular" you probably mean dynamic RAM (http://en.wikipedia.org/wiki/Dynamic_random_access_memory). This uses other tricks/tradeoffs to pack far more stuff onto the die, so you can get them down to like 1 transistor, but you have a lot more electronics to keep refreshing the memory and decoding where the voltage is. Whereas with a flip flop, you can keep the memory there without a lot of other stuff to keep refreshing the memory, so the reads are much faster.

If you need some ideas, I strongly recommend seeing if your local bookstore carries Circuit Cellar Ink (http://www.circellar.com/). If none do, they do offer electronic subscriptions (PDFs). Steve Ciarcia (http://www.circuitcellar.com/archives/priorityinterrupt/210.html) was the guy who wrote the hardware column in BYTE magazine - back when computer hobbyists built their own hardware. If you do read a copy of the magazine, be it electronic, or dead-tree-edition, pay attention to the advertisers: most of them advertise no where else, and if you're into making electronic doohickeys, they're the companies you need stuff from. Sample article (http://www.circuitcellar.com/archives/viewable/212-Ramirez/index.html) (a pdf is available from the last page of the article, but they pay attention to the referrer page so I can't link directly to the pdf). There used to be a few other magazines in this niche, but all the others that I'm aware of perished in the mid to late 90s.

OMG I have not read such techo speak since I worked in the Semi-conductor industry in a wafer fab doing defect analysis...

If you're at a university with some profs working in bioinformatics (http://en.wikipedia.org/wiki/Bioinformatics), you might be able to kill 2 birds with one stone. One of the things that they do is look for DNA sequences. BLAST (http://en.wikipedia.org/wiki/BLAST) is one of the main algorithms in use (Smith-Waterman (http://en.wikipedia.org/wiki/Smith-Waterman_algorithm) is another), and one can speed them up about 100x by moving some (http://dx.doi.org/10.1016/j.micpro.2006.04.001) of it to an FPGA (see ref #4 on the S-W wiki article). Almost all the researchers in string matching ended up moving into DNA searching back in the 80s for the Human Genome Project. A lot of the research "went dark" (stopped being published because they were working for corporations and wanted to maintain competitive advantages) at that time, and much of the remaining research went dark after 9/11 because they're using similar techniques for searching for names and contact tracing (such as this guy (http://jeffjonas.typepad.com/) - IBM bought his company and just about everything about NORA {non-obvious relation analysis} disappeared from the web).